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GNSS hardware and software technologies

GNSS Sensor Ltd provides IP cores and supporting development tools for on-chip integration of the embedded processors and proprietary satellite navigation engine.
We specialize in digital hardware design for commercial applications.

Embedded Firmware

      All of the firmware code is built around the GNU GCC toolchain offered and maintained by CPU developers (Leon3, RiscV, ARM). FW is the part of the GNSS IP and is mainly written using C++. Generally it could be splitted on two common parts:

  • Navigation specific functionality that doesn't depend of CPU type.
  • System functionality that provides interaction with the peripheries such as Timers, UART etc.

      GNSS part of the firmware implements the standardized API interface that allows easy integrate it into any platform and even build it as a separate project for the DSP simulations.

      Additionally, we provide plug-n-play functionality for any SoC allowing to detect version and generic parameters of the Hardware IP implementation. It allows to develop the single version of the Navigation library for any CPU architecture. Output binary firmware image can be directly used in ASIC development board, FPGA evaluation board with the same CPU or in the software simulator.

      For any SoC (ASIC/FPGA) implementation we provide default version of our firmware storing in ROM block, so the system is ready to use without external memory usage. Total number and types of available GNSS channels as well as additional blocks such as: Fast Search Engines and hardware Viterbi decoder are automatically detected by the Firmware which dynamically instantiates appropriate software modules to handle interaction with hardware.

      New version of the firmware or custom programs maybe directly load into internal SRAM of the SoC using SD-card controller. For this purpose we developed special BootROM function (controlled by User's pin) allowing copy the raw-image file from the formatted (FAT16) SD-card directly into SRAM and immediately execute it. This function is available in both ASIC development board and FPGA reference design.

Example of the firmware for ASIC/FPGA boards bootable from the SD-card

      In this example we show how to build simple firmware for our SoC implementation based on SPARC V8 Leon3 processor. And how to load it from the SD-card. This firmware will do simple string formatting and prints result messages into UART port. Output raw image file could be directly used in ASIC dev. board with Leon3 based SoC and any FPGA board with assembled SD-slot, like KC705. For this example we suppose that on-chip SRAM Base Addess corresponds to default entry point 0x40000000.

      Source code file main.c:

#include <stdio.h>
typedef unsigned int uint32;

void uart_write(char *s, int len)
    volatile uint32 *uart = (uint32 *)0x80000100;
    int cnt = 0;

    while (cnt < len) {
        uart[0] = (uint32)s[cnt];
        while (((uart[1] >> 20) & 0xf) != 0) {} //tx fifo counter

int main()
    volatile uint32 *uart = (uint32 *)0x80000100;
    char xstr[256];
    int len;
    int tst_cnt = 0;

    uart[3] = 75; // 70Mhz to 115200 scaler
    uart[2] = 0x3;  // rx/tx enabling

    while (1) {
       len = sprintf(xstr, "Say Hello to SD-Boot %d!\n", tst_cnt);
       uart_write(xstr, len);

    return 0;

      Makefile for our example:


CFLAGS= -c -g -Wall -msoft-float -O2 -mv8

all: sdboot_example rawimage
	echo "All done."

sdboot_example: main.o
	$(CC) main.o $(LDFLAGS) -o sdboot_example.elf

main.o: main.c
	$(CC) $(CFLAGS) main.c

	elf2raw.exe sdboot_example.elf -r -o gnsexam.raw

      Just after successful compilation do the following steps:

  • Copy the gnsexam.raw file into the root folder of the SD-card;
  • Insert sd-card into appropriate slot on the development board;
  • Switch sd_boot jumper into ON position;
  • Reboot the system by pressing Reset button;
  • Duration of the boot stage for this example is much less than 1 sec so that you should see the output messages almost at once.


  • No special hardware required for the chip programming;
  • No need to think about BOOT stage;
  • GCC toolchain;
  • Our SoC could be used as a universal platform with the customizable integrated peripheries and GPIOs;
  • Integrated Debug Support Unit and TAP-controller make available full debugging functionality via JTAG provided by CPUs developers.

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