GNSS Sensor Ltd provides IP cores and supporting development tools for on-chip integration of the embedded processors and proprietary satellite navigation engine.
We specialize in digital hardware design for commercial applications.

FPGA reference design

      We have developed powerful and flexible VHDL library that includes such modules as: configurable GNSS engine, Fast Search Engine for GPS, Glonass and Galileo systems, Viterbi decoder, internal self-test module, RF front-end control module and others. Our library is based on the following main principles:

  • Maximum independence from the CPU platform
  • Maximum flexibility using single configuration file

      We provide the following pre-build FPGA images that implement our GNSS library:

  • System-on-Chip based on 32-bits SPARC-V8 architecture with the synthesizable "LEON3" processor.
  • System-on-Chip based on 64-bits RISC-V architecture with the synthesizable "Rocket Chip" processor.
  • GNSS as the co-processor with the SPI interface.

      To support high variability of the external bus interfaces and avoid modifications in our library we implement Simplified Core Bus (SCB) and all interactions with the GNSS occurs via system-defined bridge module consisting of: bus interface module and a couple of asynchronous FIFOs:

AHB bridge

      We have developed and provide three implementations of the bridge each one for the certain architecture:

  • AHB to SCB bridge for the AMBA bus.
  • AXI to SCB bridge for "Rocket Chip" AMBA-lite bus.
  • SPI to SCB bridge for the coprocessor implementation.

      Configuration of the GNSS can vary in a wide range depending of the number of supported systems, number of channels, number of supported frequency bands and so on, but the typical implementation has the following structure:

SCB links

      Our RF front-end allows you to verify desired configuration of the GNSS library (GPS/GLONASS/Galileo L1-bandwidth) and significantly reduce the cost and simplify the development of the system-on-chip with the integrated navigation module:

SCB links

      This RF front-end implements two independent RF channels for GLONASS-L1 and GPS/Galileo/SBAS/etc-L1 bandwidths. Such RF mezzanine card with the standard LPC connector can make powerful GNSS receiver from any modern FPGA development board.

      Reference FPGA utilization is 92% on Kintex7 (xc7k325t) with the following configuration:

  • Ready-to-use GNSS receiver with the single core Leon3 CPU
  • 12 GPS + 12 GLONASS + 2 SBAS + 4 Galileo
  • Fast Search Engine GPS only.
  • SRAM 512 KB + Firmware ROM.



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